1. Field of the Invention
The present invention relates to a NAND flash memory.
2. Background Art
Data writing to a non-volatile memory cell, such as a NAND flash memory, is achieved by changing the threshold of the cell by applying a high electrical field to the cell to cause trapping of an electron into an oxide film. On the other hand, data reading is achieved by using the variation in threshold. This principle holds true for multi-level memory cells (see Japanese Patent Laid-Open Publication No. 2001-332093, for example).
As an example of prior art, a reading operation of a NAND flash memory (of shielded bit line architecture) will be shortly described.
The source line and the well of a cell are set at a potential “VSS” (0 V), and a potential “VSG” (“VDD”+“Vth”) (about 4 V), which allows transfer of “VDD” (2.5 V), is applied to the gate “BLPRE” of the n-type MOS transistor of the sense amplifier. And, a potential of 0.7 V+Vth is applied to the gate “BLCLAMP” of the n-type MOS transistor that connects the sense amplifier and the bit line to each other, thereby pre-charging the bit line of the cell to a potential of 0.7 V.
However, not all the bit lines are charged to 0.7 V. The bit lines are alternately charged to 0.7 V and 0 V, and a half of the bit lines are to be read.
During reading, a bit line amplitude occurs due to the data. Adjacent bit lines are affected by the bit line amplitude due to the capacitive coupling. Thus, the bit lines are shielded to prevent data modification by data in the adjacent cells.
After the pre-charge, the gate “BLCLAMP” is set at 0 V, and the bit lines and the sense amplifier are separated from each other.
A desired potential “VCGRV” is applied to a word line to be read, a potential “VREAD” (about 5 V), which allows turn-on without fail, is applied to the other word lines and the drain-side select gate line, and finally the potential “VREAD” is applied to the source-side select gate line.
Thus, if the cell to be read is turned on, a cell current flows, and the potential of the bit line approaches 0 V. If the cell to be read is turned off, no cell current flows, so that the potential of the bit line remains at the pre-charge voltage (0.7 V).
The gate “BLPRE” is raised again, and the node “TDC” connected to the latch circuit of the sense amplifier is pre-charged to “VDD”. After that, the gate “BLCLAMP” is set at “VSEN” (0.35 V+Vth).
Compared with the capacitance of the bit line, the capacitance of the node “TDC” is low. Therefore, when the cell is turned on, if the potential of the bit line is lower than 0.35 V, charge sharing occurs, and the potential at the node “TDC” becomes equal to the potential of the bit line.
When the cell is turned off, if the potential of the bit line is equal to 0.7 V, the transistor having the gate “BLCLAMP” remains in the off state because the threshold thereof cannot be exceeded, and thus, the potential at the node “TDC” remains at “VDD”. By raising the potential at the gate of the n-type MOS transistor between the latch circuit and the node “TDC”, the potential at the node “TDC” is transferred to the latch circuit, thereby designating H/L.
The threshold of the cell can be identified by changing the voltage “VCGRV” of the word line of the cell to be read. For example, if the cell has two thresholds, the cell can store two values. If the cell has four thresholds, the cell can store four values.
Thus, if the cell has 16 thresholds, the cell can store 16 values. To store 16 values, the retention margin of each threshold is reduced. Although the range of thresholds can be expanded to higher thresholds, higher thresholds lead to higher writing voltage and higher reading voltage.
If the writing or reading voltage increases, the writing or reading operation becomes more likely to be disturbed. As a result, there is a problem that the preset thresholds are also disturbed and shifted. The threshold shift causes erroneous reading.
Thus, it can be contemplated that, by setting a negative threshold, the retention margin can be enhanced without increasing the disturbance during reading or writing. Alternatively, this can be achieved by applying a negative potential to the word line.
However, the connection of the well is modified to enable transfer of the negative potential, and thus, the number of steps disadvantageously increases.
To overcome this disadvantage, the source line or p-type well of the cell can be biased. In this case, even if only a positive voltage is applied to the word line, the actual threshold “VGS” of the cell (the potential of the word line minus the potential of the source line of the cell) can be negative. That is, the threshold distribution can be formed also in the negative region.
However, biasing the source line or p-type well of the cell results in biasing of the source line or p-type well of other cells that don't need to be charged. Thus, there is a problem that the current consumption increases.
In addition, there is a problem that the reading or writing time increases because charging the source line or p-type well of the cell takes additional time (this is because the writing time includes the time required for verification, which is equivalent to reading, after writing).
If the source line or p-type well of the cell is not biased, only required is the charge for charging the bit line.
On the other hand, if the source line or p-type well of the cell is biased, an amount of charge is required to bias the source line or p-type well of the cell to a non-selected bit line (shielded bit line), in addition to the charge required for charging the bit line.
Biasing the source line or p-type well of the cell takes about 10 μs, for example, and therefore, the reading time increases accordingly.